In the tests and measurements performed on integrated circuits it is desirable, for reasons of cost, to be able to simultaneously test as many integrated circuits as possible with one given test setup. In order to reduce the test expense for simultaneous testing of a plurality of integrated circuits, the integrated circuits are frequently designed such that they are switchable in a test mode wherein a test sequence is executed at least partially autonomously in the integrated circuit, and wherein the number of pins, or pads, required for the test is limited per integrated circuit. Due to the fact that the test sequences are executed at least partially autonomously in the integrated circuits, however, a synchronization with the external test setup is necessary.
Various methods are possible for synchronizing the test sequences with the external test setup. One possibility is to operate the integrated circuits to be tested and the test setup with a clock shared by them, and to track the execution of the clock sequence in the integrated circuits by a clock counter in the test setup. In order to be able to track the test sequence in the integrated circuits, it must be known, for the test setup, after how many clocks the integrated circuits are in which state, wherein all test modes of the integrated circuits must be checked for the number of clocks required prior to their use in the test.
A further possibility of synchronization is that the integrated circuits comprise a specific synchronization pin outputting a signal to the test setup at desired points in time. To this end, the external test setup must consequently have a test interface for the synchronization pin of each integrated circuit to be tested so as to be connected to same. In addition, the external test setup must check whether the synchronization signal being sent is faulty, while it is taken into account that individual ones of the integrated circuits to be tested may be defect and therefore do not send any synchronization signal at all or do not send a permanent one.
A further possibility for synchronizing the external test setup with the integrated circuits to be tested is that the integrated circuits to be tested also have a synchronization pin connected to the test setup, and send a specific protocol to the external test setup via same, from which protocol the synchronization may be derived. This solution for synchronization, however, limits the flexibility of the data transfer and prolongs transfer time. As is also the case in the previous approach, the test setup must further verify the specific protocol sent of each integrated circuit to be tested for any faultiness so as to take into account the possibility of defect integrated circuits.
FIG. 2 shows a test arrangement wherein each integrated circuit to be tested has a synchronization pin, and wherein the synchronization pin of each integrated circuit to be tested, or of each integrated device to be tested (DUT= device under test) 300, 302, 304, 306, 308, 310, 312 and 314 is connected to an external test setup 316. Each integrated circuit to be tested 300–314 is represented in an exemplary manner so as to comprise a terminal Vcc1 for receiving a supply voltage, a terminal GND so as to be connected to ground, and three terminals a1, a2 and a3, which, during the test mode of the integrated circuits 300–314, output the test data produced during the test mode and, if need be, receive data from the external test setup 316. In addition, each integrated circuit to be tested 300–314 has a synchronization pin a4 where a synchronization signal is output which is synchronous with the test sequence executed during the test mode. The test setup 316 includes a plurality of test interfaces 318, 320, 322, 324, 326, 328, 330, and 332, each of which is connected to the three test pins a1–a3 of an integrated circuit to be tested 300–314. Further the external test setup 316 includes a plurality of interfaces 334, 336, 338, 340, 342, 344, 346, and 348, each of which is connected to the synchronization pin a4 of an integrated circuit to be tested 300–314.
During a simultaneous test of the eight integrated circuits 300–314, the external test setup 316 puts each of the integrated circuits 300–314 in a test mode, wherein the integrated circuits 300–314 output test data at the pins a1–a3, which is produced during a test sequence executed on them, and output synchronization signals at the synchronization pin a4, which signals are synchronous with the test sequence. The test setup 316 receives the test data at the test interfaces 318–332 and evaluates them in a suitable manner. For synchronizing the evaluation with the test sequences executed on the integrated circuits 300–314, the test setup 316 uses the eight synchronization signals which it receives at the interfaces 334–348. The test setup 316 must carry out a check for each synchronization signal to see whether the synchronization signal has been produced by a defect or a functional integrated circuit 300–314.